/*!
    \file    usbd_hw.h
    \brief   usbd hardware configure file

    \version 2020-08-01, V3.0.0, firmware for GD32F30x
    \version 2022-06-10, V3.1.0, firmware for GD32F30x
*/

/*
    Copyright (c) 2022, GigaDevice Semiconductor Inc.

    Redistribution and use in source and binary forms, with or without modification, 
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this 
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice, 
       this list of conditions and the following disclaimer in the documentation 
       and/or other materials provided with the distribution.
    3. Neither the name of the copyright holder nor the names of its contributors 
       may be used to endorse or promote products derived from this software without 
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
OF SUCH DAMAGE.
*/

#ifndef __USBD_CONF_H
#define __USBD_CONF_H

#include "gd32f30x.h"


#define USBD_CFG_MAX_NUM                    1
#define USBD_ITF_MAX_NUM                    7


/* bInterfaceNumber */
#define CDC1_ACM_CMD_INTERFACE              0
#define CDC1_ACM_DATA_INTERFACE             1
#define CDC2_ACM_CMD_INTERFACE              2
#define CDC2_ACM_DATA_INTERFACE             3
#define CDC3_ACM_CMD_INTERFACE              4
#define CDC3_ACM_DATA_INTERFACE             5
#define USBD_MSC_INTERFACE                  6


/* endpoint count used by the X device */
#define EP_COUNT                            8

#define CDC1_ACM_CMD_EP                     EP_IN(1)
#define CDC1_ACM_DATA_IN_EP                 EP_IN(2)
#define CDC1_ACM_DATA_OUT_EP                EP_OUT(2)

#define CDC2_ACM_CMD_EP                     EP_IN(3)
#define CDC2_ACM_DATA_IN_EP                 EP_IN(4)
#define CDC2_ACM_DATA_OUT_EP                EP_OUT(4)

#define CDC3_ACM_CMD_EP                     EP_IN(5)
#define CDC3_ACM_DATA_IN_EP                 EP_IN(6)
#define CDC3_ACM_DATA_OUT_EP                EP_OUT(6)

#define MSC_IN_EP                           EP_IN(7)
#define MSC_OUT_EP                          EP_OUT(7)

/* bEndpoint data size */
/* 因为内存占用比较多，所以需要把 USBD_EP0_MAX_SIZE 设置为16，以减小接口0的空间，而给用户接口使用 */
#define CDC_ACM_CMD_PACKET_SIZE             8
#define CDC_ACM_DATA_PACKET_SIZE            32
#define MSC_DATA_PACKET_SIZE                64

/* endpoint0, Rx/Tx buffers address offset */
#define EP0_TX_ADDR                         0x40
#define EP0_RX_ADDR                         0x50

/* CDC1 command Tx buffer address offset */
#define CDC1_ACM_INT_TX_ADDR                0x60
/* CDC1 data Tx/Rx buffer address offset */
#define CDC1_ACM_BULK_TX_ADDR               0x70
#define CDC1_ACM_BULK_RX_ADDR               0x90

/* CDC2 command Tx buffer address offset */
#define CDC2_ACM_INT_TX_ADDR                0xB0
/* CDC2 data Tx/Rx buffer address offset */
#define CDC2_ACM_BULK_TX_ADDR               0xC0
#define CDC2_ACM_BULK_RX_ADDR               0xE0

/* CDC3 command Tx buffer address offset */
#define CDC3_ACM_INT_TX_ADDR                0x100
/* CDC3 data Tx/Rx buffer address offset */
#define CDC3_ACM_BULK_TX_ADDR               0x110
#define CDC3_ACM_BULK_RX_ADDR               0x130

/* MSC data Tx/Rx buffer address offset */
#define MSC_BULK_TX_ADDR                    0x180
#define MSC_BULK_RX_ADDR                    0x1C0

/* MSC config */
#define MEM_LUN_NUM                         2
#define MSC_MEDIA_PACKET_SIZE               4096


/* base address offset of the allocation buffer, used for buffer descriptor table and packet memory */
#define BTABLE_OFFSET                       (0x0000)

#endif /* __USBD_CONF_H */
